1. Field of the Invention
The present invention relates, generally, to a printed circuit board (PCB) having an RF module power stage circuit embedded therein, and more particularly, to a PCB having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.
2. Description of the Related Art
In order to correspond to requirements for miniaturization and high functionality of electronic products according to the recent development of electronic industries, electronic techniques have been developed to insert a resistor, a capacitor, and an IC (Integrated Circuit) into a substrate.
Although a discrete chip resistor or a discrete chip capacitor has been mounted on the surface of a PCB to date, the development of PCBs in which passive devices such as resistors or capacitors are embedded has been under study in recent years.
That is, techniques for fabricating a PCB having an embedded passive device are intended to substitute for a conventional chip resistor or chip capacitor by inserting a passive device into the outer layer or inner layer of the PCB using new materials and processes.
In the PCB having an embedded passive device, in which the passive device is inserted into the outer layer or inner layer of the PCB, when the passive device is incorporated into part of the PCB regardless of the size of the PCB, it is referred to as an ‘embedded passive device’. Such a substrate is called an ‘embedded passive device PCB’.
The most important characteristic of the embedded passive device PCB is that the passive device, such as the resistor or capacitor, is intrinsically provided in the PCB, without the need for mounting a discrete passive device on the surface of the PCB.
According to technical trends of embedded passive device PCBs in recent years, thorough research into techniques for realizing an embedded decoupling capacitor in a flip chip package substrate for high-speed products has been conducted. In this regard, a method of fabricating a flip chip substrate having an embedded capacitor was disclosed in U.S. Pat. No. 6,407,929, which was granted to Intel Corporation.
FIGS. 1A to 1K illustrate a process of fabricating a flip chip substrate having an embedded capacitor, which was patented by Intel Corporation.
FIGS. 1A to 1E illustrate a process of fabricating a silicon chip capacitor, and FIGS. 1F to 1K illustrate a process of fabricating a package substrate including an embedded capacitor by mounting the capacitor in the package.
As shown in FIG. 1A, a silicon substrate 101 is prepared, and as shown in FIG. 1B, titanium or titanium nitride is deposited on the silicon substrate 101 to form a barrier layer 102.
As shown in FIG. 1C, platinum, palladium, tungsten, or AlSiCu is deposited on the barrier layer 102 to form a silicon chip capacitor lower electrode 103 having a thickness of 1˜10 μm.
As shown in FIG. 1D, material having a high dielectric constant, such as SrTiO3, BaTiO3, Pb(Zr)TiO3, or Ta2O5, is deposited on the lower electrode 103, thus forming a capacitor dielectric layer 104 having a thickness of 100˜1000 Å.
As shown in FIG. 1E, the upper electrode 105 of the silicon chip capacitor is formed on the dielectric layer 104 using the same process for forming the lower electrode 103 of the silicon chip capacitor.
Subsequently, the silicon chip capacitor, having a thickness of 30˜150 μm, is mounted on an electronic package having a plurality of via holes and conductive material deposited thereon, after which an insulating layer is formed, thus fabricating a flip chip package having an embedded silicon chip capacitor.
That is, as shown in FIG. 1F, the flip chip package substrate, having an electronic inner circuit in which the plurality of via holes is formed and the conductive material is deposited, is provided, and the silicon chip capacitor is mounted thereon, as shown in FIG. 1G.
In FIG. 1H, an insulating layer 109 having a thickness of 80˜150 μm is formed on the silicon chip capacitor mounted in FIG. 1G.
In FIG. 1I, the insulating layer 109 is subjected to laser cutting to form via holes 110 having a diameter of 50˜300 μm.
In FIG. 1J, in order to electrically connect the upper electrode 105 of the silicon chip capacitor, conductive material 112 is deposited. FIG. 1K is a cross-sectional view showing the electronic package provided with an embedded capacitor using a build-up process.
In addition to U.S. Pat. No. 6,407,929, granted to Intel Corporation, conventional techniques related to the embedded passive device PCB comprise Japanese Patent Laid-open Publication No. 1995-115277 regarding ‘layered ceramic part’, Japanese Patent Laid-open Publication No. 2002-344146 regarding ‘high-frequency module and fabrication method thereof’, and Japanese Patent Laid-open Publication No. 2004-056144 regarding ‘printed circuit board’.
Such conventional techniques are used to realize an embedded decoupling capacitor in a flip chip package substrate for high-speed products. However, techniques for embedding a resistor or bead linked with a decoupling capacitor in order to improve the performance of the power stage of an RF IC having a high degree of integration are not well developed yet.